Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. Generally, these can be considered either volatile or non-volatile memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
The manufacturing of memory devices typically includes a testing operation such as the testing standard IEEE 1149.1, also known as Joint Test Action Group (JTAG) boundary scan testing. The JTAG boundary scan method comprises a boundary scan cell coupled to predetermined pins of the integrated circuit. Test data is input to one or more boundary pins of the circuit. Another boundary pin or pins of the circuit are then checked for a predetermined output signal. Since the functions and topology of the tested part are known, the output signal will be known.
This testing can be a complicated, time consuming process. As memory devices become increasingly more complex and the memory density increases, the cost for testing also increases. Since the memory manufacturer has to test a large number of memory devices, even a small increase in test time, multiplied by the large number of memory devices, creates a problem for the manufacturer.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce the time required to test a large number of integrated circuits.